1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and in particular to a synchronous semiconductor memory device operating in synchronization with an external clock signal.
2. Description of the Background Art
With increase in operation speed of microprocessors (which will be referred to as xe2x80x9cMPUsxe2x80x9d hereinafter) in recent years, synchronous DRAMs (which will be referred to as SDRAMs hereinafter) and others operating in synchronization with clock signals have been used for achieving fast access of dynamic random access memories (which will be referred to as xe2x80x9cDRAMsxe2x80x9d hereinafter) and others used as main storage devices.
Internal operations of the SDRAM and others are controlled by dividing the operations into the row-related operation and the column related operation for control.
In the SDRAMs, structures in which a memory cell array is divided into banks each allowing independent operation have been employed for allowing further fast operation. In each bank, the row-related operation and the column-related operation are controlled independently of each other.
As a result of increase in operation speed, the semiconductor memory devices such as SDRAMs suffer from the following problems during operation tests in manufacturing steps or outgoing tests.
With increase in storage capacity of the semiconductor memory device, a time required for the test increases, resulting in increase in cost for the test and increase in manufacturing cost of the product.
As countermeasures against increase in test time which is caused by the increased storage capacity of the semiconductor memory device, such a manner has first been employed that the test is carried out in parallel on a plurality of semiconductor memory devices for improving the test efficiency. However, the foregoing increased storage capacity of the semiconductor memory device increases the number of bits of an address signal applied to the semiconductor memory device, number of bits of a data I/O interface and others, and thus increases the numbers of input pins and I/O pins for the control signals in each semiconductor memory device. This restricts the number of semiconductor memory devices, which can be simultaneously tested in parallel.
The number of chips of the semiconductor memory devices, which can be simultaneously measured by one test operation of a tester device, depends on a relationship between the number of pins provided in a tester side and the number of pins required in the chip side, and can be generally expressed by the following formula:
(number of pins of tester)/(number of pins required in chip) greater than (number of pins allowing simultaneous test)
Further, an extremely expensive tester device is required for increasing an operation speed of the tester device in accordance with an increased operation speed of the semiconductor memory device itself. This also increases the test cost.
An object of the invention is to provide a synchronous semiconductor memory device which allows an easy simultaneous parallel test even if the device has an increased storage capacity.
Another object of the invention is to provide a synchronous semiconductor memory device, which can reduce a load on a tester side and allows an inexpensive operation test even if a fast operation is to be performed.
In summary, the invention provides a synchronous semiconductor memory device for taking in an address signal. and a control signal in synchronization with an external clock signal, including a memory cell array, an internal clock producing circuit, an address signal input circuit, a memory cell select circuit, a data I/O node and an interface circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns.
The internal clock producing circuit controls a synchronous operation of the synchronous semiconductor memory device. The internal clock producing circuit produces a first internal clock signal of the same frequency as the external clock signal in a first operation mode, and produces the first internal clock signal and a second internal clock signal synchronized with the external clock signal and having a higher frequency than the external clock signal in a second operation mode.
The address signal input circuit takes in the address signal in synchronization with the first internal clock signal.
The memory cell select circuit operates in synchronization with the first internal clock signal in the first operation mode and in synchronization with the second internal clock signal in the second operation mode, and selects the memory cells of at least n (n: natural number) in number during one write cycle in accordance with the address signal.
The data I/O node is supplied with write data to be written into the memory cell or read data read from the memory cell.
The interface circuit is arranged between the memory cell selected by the select circuit and the data I/O node, and transmits the write data. The interface circuit holds data of at least n in number applied in serial to the I/O node, and operates in synchronization with the first internal clock signal in the first operation mode and in synchronization with the second internal clock signal in the second operation mode to apply in parallel the write data to the selected memory cells.
According to another aspect of the invention, a synchronous semiconductor memory device for taking in an address signal and a control signal in synchronization with an external clock signal includes a memory cell array, an internal clock producing circuit, an address signal input circuit, a memory cell select circuit, a data I/O node and an interface circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns.
The internal clock producing circuit produces an internal clock signal for controlling a synchronous operation of the synchronous semiconductor memory device.
The address signal input circuit takes in the address signal in synchronization with the internal clock signal.
The memory cell select circuit operates in synchronization with the internal clock signal to select the memory cell in accordance with the address signal.
The data I/O node is supplied with write data to be written into the memory cell or read data read from the memory cell.
The interface circuit is arranged between the memory cell selected by the select circuit and the data I/O node, and transmits the write data. The interface circuit holds a plurality of data applied to the I/O node, and operates in a test mode to produce, as the write data, a test data pattern by decoding the plurality of data and apply the write data to the selected memory cell.
According to still another aspect of the invention, a synchronous semiconductor memory device for taking in an address signal and a control signal in synchronization with an external clock signal includes a memory cell array, a first internal clock producing circuit, a memory cell select circuit and an I/O circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns.
The first internal clock producing circuit controls a synchronous operation of the synchronous semiconductor memory device. The first internal clock producing circuit receives complementary clock signals including first and second clock signals having a constant phase difference therebetween, and produces an internal clock signal having an active period corresponding to the phase difference.
The memory cell select circuit selects the memory cell in synchronization with the internal clock signal.
The I/O circuit transmits data to and from the memory cell selected by the select circuit.
According to yet another aspect of the invention, a synchronous semiconductor memory device for taking in an address signal and a control signal in synchronization with an external clock signal includes a memory cell array, an internal clock producing circuit, a memory cell select circuit and an I/O circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns.
The internal clock producing circuit controls a synchronous operation of the synchronous semiconductor memory device. The internal clock producing circuit produces an internal clock signal having an active period independent of a period of the external clock signal in response to activation of the external clock signal.
The memory cell select circuit selects the memory cell in synchronization with the internal clock signal.
The I/O circuit transmits data to and from the memory cell selected by the memory cell select circuit.
Accordingly, the invention can achieve the following advantage. In the second operation mode, since an internal processing speed of the device can be increased as compared with a data write speed, a load on a test in a test operation can be reduced, and further a fast operation test can be carried out on the synchronous semiconductor memory device.
The invention can also achieve the following advantage. Since the data pattern is internally produced based on the external data in the test operation mode, a load on the tester can be reduced.
Further, the invention can achieve the following advantage. In the test mode, the speed of internal processing of the device can be increased so that a load on the test in the test operation can be reduced, and further a fast operation test of the synchronous semiconductor memory device can be performed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.